1. Field of the Invention
The present invention generally relates to a method for fabricating a semiconductor device, in particular, to a method for fabricating a device pattern.
2. Description of Related Art
As the integration of semiconductor devices has been increasingly enhanced, the size of a circuit device is generally reduced according to a design rule about reducing the volume in the process for fabricating an integrated circuit (IC) device. However, although the line width and line pitch of the wire are continuously reduced, they are still restricted to a certain extent. For example, a lithography process has an exposure limit, so that an insufficient resolution is resulted, and thus, the current line width and line pitch can merely be reduced to a certain level.
When a comb-shaped pattern is fabricated, it is still difficult to reduce the line pitch between two wires. In the prior art, a line by spacer fill (LBSF) method is provided to form a third wire between two wires, so as to effectively reduce the line pitch between the two wires. However, the LBSF method is not applicable to the fabrication of a comb-shaped pattern due to the following reason. When the LBSF method is adopted to fabricate a comb-shaped pattern, the third wire subsequently formed between the former two wires is unable to be connected to the comb-shaped pattern, such that a comb-shaped pattern with a line pitch smaller than the exposure limit cannot be formed.